RenumKiCadPCB V0.352 on Github

I just uploaded V0.352 to Github. This (hopefully) fixed a bug where the system could chose the wrong “Top Layer”. It also (hopefully) corrected an issue with the undocumented AR field in the schematic. The field is not only undocumented, as implemented it can lead to “ghost” components in the file which are not visible to eeSchema or PCBNew. This, in turn led to errors in renumbering which could previously only be corrected by manually editing the schematic file with a text editor.

Although I have tested the code on my system I have not received feedback with respect to whether it works (or builds) for others.

I am re-writing RenumKiCadPCB from scratch in c++. I am doing so in order to learn c++ and wxWidgets and then create a GUI version of the program. Doing so may provide enough of a grounder to produce a version of eeSchema and/or PCBNew with integral renumbering. It should be quite easy to do this once I get the hang of a few parts of the KiCad source. The developers would like to see renumbering “pushed” from PCB to schematic via a netlist update. This probably makes sense in the broader context of things like pin swapping but since no progress has been mode in this direction it will have to work.

I intend to add a number of features to V0.400 (which I might release before V0.500, the GUI version). These are:

  1. Enable global change to module text angle;
  2. Enable global change to module text location (i.e. align Value and/or User with Ref, center the text fields on the module;
  3. Generate a Was/Is file from the PCB;
  4. Update schematic only using a Was/Is file.

The last two items may seem odd but it looks like updating the schematic only and then using eeSchema to update the PCB using timestamps regenerates the PCB and the netlist directly using KiCad internal functions so this would be a stepping stone to full integration, or at least less likelihood of RenumKiCadPCB getting out of sync with the file formats which appear to evolve and not be well documented. The net result of was/is generation followed by update PCB is substantially identical to pushing a netlist from PCB to schematic.

I would greatly appreciate any feature suggestions, bug reports, or general encouragement.

 

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